1. Field of the Invention
The present invention relates to differential signal drivers, and in particular, to low voltage differential signal (LVDS) driver circuits.
2. Related Art
Many integrated circuits (“chips”) drive signals to and receive signals from other chips across a variety of signal media and media lengths. Typically, the signal media, e.g., cables, are designed to have a transmission line impedance of 50 ohms, which is typically matched to the output impedance of the transmitter and input impedance of the receiver. One example of the circuit used to drive such signals is an LVDS circuit, which is primarily used in short range applications, e.g., inter-chip signals on printed circuit boards. As is well known, advantages of LVDS circuits include high bandwidth, low power, reduced EMI (electromagnetic interference) effects, and better immunity to common mode noise.
Referring to FIG. 1, a typical LVDS circuit 10 includes a pre-driver stage 12 and output stage 14 for driving current through the load impedance 16 (typically a resistance of 100 ohms), the voltage across which is sensed by a receiver circuit 18 in accordance with well known principles. The data to be transferred arrives in the form of a differential signal 11c having opposing positive 11p and negative 11n signal phases. In response to this signal 11c, the pre-driver stage 12 produces a corresponding differential drive signal 13, also having opposing signal phases 13p, 13n, which the output stage 14 uses to produce the LVDS output signal 15 with its own opposing signal phases 15p, 15n. This signal 15 produces the load current 15i for conduction by the load impedance 16.
The power supply VDD provides a supply current 11a for the pre-driver stage 12 and a supply current 11b for the output stage 14. The output stage supply current 11b includes supply current Id for the output stage 14, as well as the current Iload needed for driving the load impedance 16. The amount of supply current consumed by the pre-driver stage 12 and output stage 14 can be, and often is, significant relative to the load current Iload.
Referring to FIGS. 2A and 2B, two forms of output stages 14 are typically used: voltage mode (FIG. 2A), and current mode (FIG. 2B). As is well known, the voltage mode driver 14a has the advantage of low power, but often provides poor line impedance matching. In contrast, the current mode diver 14b has the advantage of good line impedance matching, but generally consumes higher power.
Referring to FIG. 3, one example of a conventional current mode output stage 14a includes NPN bipolar junction transistors Q1, Q2, resistances R1, R2, and a current source 20a, interconnected substantially as shown. Each of the resistances R1, R2 is substantially equal to 50 ohms so as to be half of the 100 ohm impedance of the load 16. In such a circuit 14a, current I1 is equal to the load current 15i (I1=Iload), while current I2 is equal to three times the load current 15i (12=3*Iload). As a result, the current source 20a must provide four times the amount of the load current so as to provide sufficient current for operation of the output stage 14a and sufficient current 15i for the load 16. Additionally, the signals 13p, 13n provided by the pre-driver stage 12 (not shown) must have sufficient drive current capacity to drive the large base-emitter capacitances of the transistors Q1, Q2.
Referring to FIG. 4, another example of a conventional current mode output stage 14b includes PMOS transistors P1, P2, NMOS transistors N1, N2, and current source circuits 20bp, 20bn, and a resistance R, all interconnected substantially as shown. In this circuit 14b, the resistance R is substantially equal to the load impedance of 100 ohms. Each of the two branch currents I1, I2 is equal (mutually exclusively in time) to two times the load current 15i (I1=I2=2*Iload). While this current is less than the current for the circuit of FIG. 3, additional current Ipd will still be required for the pre-driver stage 12 (not shown).
Referring to FIG. 5, another example of a conventional voltage mode output stage 14c is biased between two voltage potentials, Vhigh, Vlow rather than current sources, and does not require the internal resistance R. Accordingly, the two supply currents I1, I2 are needed during mutually exclusive time intervals and each one is equal to the load current 15i (I1=I2=Iload). However, the output impedance of this output stage 14c is dependent upon the channel characteristics of the individual transistors P1, P2, N1, N2, and, therefore, cannot be matched well to the 50 ohm impedance of the signal transmission medium and load 16. Accordingly, some form of calibration must be provided, e.g., in control of the device characteristics during manufacture or additional calibration circuitry.
Referring to FIG. 6, another example of a conventional voltage mode output stage 14d includes the transistors P1, P2, N1, N2 of the circuit of FIG. 5, plus resistances R1a, R2a, Rib, R2b, all interconnected substantially as shown. Each of the resistances R1a, R2a, R1b, R2b is 50 ohms so as to be half of the 100 ohm load impedance 16. Similar to the circuit 14c of FIG. 5, each of the mutually exclusive currents I1, I2 is equal to the load current 15i (I1=I2=Iload). Improved matching between the output stage impedance and the signal transmission medium is provided by the resistances R1a, R2a, R1b, R2b. However, this then requires the channel impedances of the transistors P1, P2, N1, N2, when in their turned-on states, to be as close to zero ohms as possible. As a result, the signals 13p, 13n provided by the pre-driver stage 12 (not shown) must be capable of driving the larger input capacitances at the gate electrodes of the transistors P1, P2, N1, N2.
Accordingly, it would be desirable to have a differential signal driver circuit topology that minimizes the amount of supply current needed, while also avoiding large input capacitances, as well as proper matching between the impedances of the output driver circuit and signal transmission medium.